1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which the period of time required for refreshing can be reduced.
2. Description of the Prior Art
Currently, a dynamic RAM (hereinafter, abbreviated as "DRAM") is used as a semiconductor memory device with the greatest memory capacity, but its integration remains to be increased. In a DRAM, data are stored in memory cells using their capacitance. Because of this principle of holding data in memory cells, memory cells must be refreshed. Failure to refresh the memory cells results in the destruction of data stored in these cells. Further, the period of time for performing the refresh is prolonged with the advancement of the integration of a DRAM. Therefore, it has been demanded to shorten the period of time required for the refresh. Hereinafter, this period of time is referred to as "refresh overhead time".
The refresh operation in a memory cell will be described with reference to FIGS. 13 and 14. In FIG. 14, shown are a memory cell MA, a sense amplifier SA, a word line W, a pair of bit lines b and /b, and a sense amplifier control circuit PLC. When the word line W is activated, data stored in the memory cell MA is read out to the pair of bit lines b and /b, and the sense amplifier SA is activated so that the read out data is amplified. Then, the amplified data is written back into the memory cell MA, thereby completing the refresh. In this way, the refresh is performed for each memory cell MA connected to the word line W, and therefore the length of the refresh overhead time depends on the number of word lines.
Referring to FIGS. 15-18, the refresh operation in a conventional semiconductor memory device will be described in more detail. The memory device shown in FIG. 15 comprises an input/output unit I/O, a pair of data lines D and /D, a memory block MB, a row decoder control circuit ROC, a column decoder control circuit COC, a row decoder control line RA, a column decoder control line CA, and a control line for a sense amplifier power source control circuit PLCL. The internal structure of the DRAM is illustrated in more detail in FIG. 16. In FIG. 16, CO is a column decoder, ROW is a row decoder, PLC is a sense amplifier power source control circuit, SA.sub.1 -SA.sub.n are sense amplifiers, SW.sub.1 -SW.sub.n are switching elements, SWC.sub.1 -SWC.sub.n are switching element control lines, b.sub.1 -b.sub.n and /b.sub.1 -/b.sub.n are bit line pairs, PL.sub.1 is a first sense amplifier power source line, PL.sub.2 is a second sense amplifier power source line, and W.sub.1 -W.sub.n are word lines.
In the DRAM shown in FIGS. 15 and 16, the refresh is performed sequentially from the memory cell MA connected to the word line W.sub.1 to the one connected to the word line W.sub.n, in a predetermined unit of time, so that data are continuously rewritten in the memory cells. When the level of integration of a DRAM becomes higher, however, the refresh overhead time becomes longer, resulting in a shortening of the period of time for reading and writing data. More specifically, when comparing two memory devices one of which is greater in storage capacity by four times than the other, the refresh overhead time in the greater memory device ((b) of FIG. 17) is four times as long than the refresh overhead time ((a) of FIG. 17) in the smaller memory device. In a special type of DRAM such as a video memory, particularly, data in all memory cells must be sequentially read out and written, and, therefore, it is not possible to access all memory cells during the time when memory cells can retain their data, resulting in that the refresh times must be provided as shown in (b) of FIG. 18. If a DRAM has a small storage capacity, it is not necessary to provide such a refresh overhead time ((a) of FIG. 18).
As the level of integration of a DRAM becomes higher, the number of memory cells increases so that the refresh overhead time which is useless for the reading or writing operation is prolonged. To alleviate this problem, the number of refresh times is reduced in a highly integrated DRAM. This can be realized by improving the performance of memory cells, i.e., by lengthening the data hold time of the memory cells. In view of the recent strides in integration, however, further improvement of the performance of memory cells is nearly impossible. Hence, it is necessary to shorten the refresh overhead time.
In a DRAM, usually, memory cells are divided into several blocks as shown in FIG. 19. The DRAM of FIG. 19 comprises a row address decoder 201 for decording an external address signal, a refresh address counter 202 for generating a refresh address, an address change circuit 209; and memory blocks MB.sub.A and MB.sub.B. The memory block MB.sub.A includes a memory cell unit 203 and sense amplifiers 205. The other memory block MB.sub.B includes a memory cell unit 204 and sense amplifiers 206. The address change circuit 209 changes an external address signal and an internal refresh address in accordance with a refresh request signal which is supplied when the refresh is to be performed.
The row address decoder 201 decodes an external address signal, and a write/read address is input to the address change circuit 209. The refresh address counter 202 generates an internal refresh address signal which is then supplied to the address change circuit 209. According to a refresh request signal, the address change circuit 209 changes the write/read address and the internal refresh address. In a write/read cycle, the address change circuit 209 outputs only a write/read address. This causes the corresponding word line in one memory block to be activated, and the potential change is amplified by a sense amplifier to write or read a memory cell. When the word line of the memory block MB.sub.A is activated and the write or read is done in the memory block MB.sub.A, the word line of the address of the other memory block MB.sub.B is not activated and the refresh of the address is not performed. When the refresh is to be performed, the refresh address counter 202 outputs the internal refresh address through the address change circuit 209. Then, the word lines of both the memory blocks MB.sub.A and MB.sub.B are simultaneously activated, and the potential changes on the word lines are amplified to refresh the memory cells of the address. After the refresh of the memory cells connected to one word line in both the memory blocks MB.sub.A and MB.sub.B is completed, the refresh address of the refresh address counter 202 is changed, and the refresh of the memory cells of the new refresh address is performed. In this way, all memory cells in the memory blocks MB.sub.A and MB.sub.B are sequentially refreshed.
When a memory block of a conventional DRAM is written or read, the refresh of a row address of other memory blocks in the DRAM cannot be performed. Therefore, the refresh overhead time is required for all word lines to refresh memory cells connected thereto, resulting in that the period of time for writing and reading is reduced.